Risc-v assembly track

Exercism
1

Hello!

I would like that a risc-v assembly track be offered!

Would you like it too?

Thank you!

2

That would be cool! Now we just need someone willing to build and maintain the track :smile:

Are you interested in building a risc-v track? Does the MIPS track count as a RISC-V track?

3

Hello!

Sorry, but I meant I would like to try and learn a bit about risc-v assembly.
I can’t maintain a track!
Maybe there’s someone who has the knowledge to make it happen…

Thank you for your response.!

4

The MIPS track says,

MIPS is a reduced instruction set computer (RISC) instruction set architecture, currently used mostly in video game consoles and routers. It is also a popular architecture in introductory courses and textbooks on computer architecture, due to its simplicity relative to x86 and ARM. Here we use the 32-bit instruction set; a 64-bit instruction set also exists.

Is that what you’re looking for?

5

I would like to have a place to try my hand at https://riscv.org/ assembly!

6

RISC-V is a RISC standard. MIPS is an implementation of RISC assembly. You can practice assembly that (very closely) implements the RISC-V standard on the MIPS track.

1 Like
7

Does the MIPS track count as a RISC-V track?

Sorry for necromancing a relatively old topic, but IMHO, not really.

There are several differences:

  • conditional branching instructions are different between the two (direct branching instructions in RISC-V vs. compare + branching on register set by comparison in MIPS)
  • the number of argument and temporary registers
  • separate return value and argument registers (MIPS) vs shared ones (RISC-V)

Also, MIPS (the company) stopped producing MIPS (the processor architecture) and is now a “Strategic Member” of RISC-V International:

So while they are certainly related, they are not interchangeable. RISC-V is an open ISA with a bright future whereas MIPS as an independent architecture is pretty much dead.

1 Like
8

Hello,

This caught my attention because i am also very interested in a RISC-V track. Since this seems to suggest that a RISC-V track is actually more relevant than the already existing MIPS track, i want to ask if there are any code changes or work being made towards this?

thank you !

1 Like
9

I’m not aware of/involved in any work related to a RISC-V track. I do still believe that it would be worthwhile (potentially replacing the MIPS track though I’m not sure Exercism ever phased out a track). I’m not sure if anyone at this point still makes CPUs with the MIPS ISA, Longsoon may have been the last company to do so and they switched to their own ISA (Loongarch) for all their CPUs manufactured after 2019.

10

Tracks can exist side by side if they are not broken.

2 Likes
11

I could help in managing a RISC-V track, if you’re looking for people. Porting from the MIPS and x86-64 assembly would be a good place to start from, and shouldn’t be too difficult. The main question is mostly how many extensions it should support (starting with either RV32IG would be a good start, but at the same time only using the basic RV32I would be a good challenge).

The MIPS track definitely doesn’t count though. RISC is a class of processor; MIPS, ARM, and RISC-V are all RISC processors, but they have very different aims and design goals.

1 Like
12

For an online test runner on x86-64 servers, which emulator would be used?

All of the arm64 exercise tests are generated. For the test generator and exercise tests, I would start from there. (See arm64-assembly-test-runner issue #8 for the current status of that track.)

Would you like to look through the steps in add-first-exercise and create a simple prototype github repo with hello-world?

13

QEMU works well for RISC-V emulation. Some more options for you are over here. QEMU’s how Debian does things to my knowledge for their package porting. I’ll take a peek at the stuff you’ve linked, see what I can contribute!

1 Like
14

Would a 32-bit or a 64-bit track be more helpful/fun for our students?

I expect off-the-shelf hardware will support 64 bits, but a typical FPGA CPU design for engineering students will only have 32 bits.

From Patterson and Hennessy’s
Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Edition 2

With this edition…, we switched from 64-bit RV64 to 32-bit RV32. Instructors found that the extra complexity of a 64 bit instruction set made it harder on the students. RV32 reduces the core architecture by 10 instructions … and they don’t have to understand operations on the lower 32 bits of a 64-bit register.

15

That depends on the spec of processor you’re looking into. A “”“full”“” RISC-V processor, capable of running Linux is generally going to be a multi-core, RV64G processor (which includes the extensions for Multiply, Atomic operations, single and double-precision floating point, Control and Status Registers, and memory fences). Microprocessors could run RV32G, or even a 16-register variant RV32E.

All the key portions of the RISC-V instruction set are summarised in the RV32I base, with many of the common extensions falling within RV32G. The conversion from RV32 and RV64 is relatively trivial, and RV32 is more simplistic while still containing all of the necessary structural knowledge for assembly operations.

In summary, I think it would be best to build a 32-bit track, with later-stage problems using the G extension set.

1 Like
16

I created a sample Hello World repo.

That is 64-bit for now; it wasn’t difficult to get working on my local x86_64 Ubuntu 22.04.5 LTS

I’m not sure what the equivalent of arm64’s ci.yml would be if we target 32-bit. Makefile should only need trivial changes.