Can we work on adding a System Verilog/Verilog track?

Hello! I am sort of new to this site, and I have loved learning Python with it, the community responses help me see how other libraries (other than those covered in the exercise) could be utilized, which is great! I think SystemVerilog would be a great addition to this site since it now incorporates A LOT from C/C++/Java and a lot of electrical engineers posing as computer engineers/CS may find that useful. It interacts directly with hardware, which is a little different from most of the other languages here, but there is such a large space for basic improvements that I myself am not sure how to implement, but would love community feedback with!

The good news is: There is a Verilog track in the works. The bad news is, that it is probably abandoned.

Building a track is quite a bit of work, but it is a rewarding experience. It also needs a lot of time to maintain it. If you want to participate in the track, I recommend that you read the respective doc section.

@rca0017 Thanks for your interest! If you’d like to take the work on, I suggest posting a list of the tasks you intend to complete here (e.g. choosing exercises, adding exercises, adding a test runner if there’s not one), getting agreement from @ErikSchierboom on that plan, and then we’ll add you as a maintainer.