Risc-v assembly track


I would like that a risc-v assembly track be offered!

Would you like it too?

Thank you!

That would be cool! Now we just need someone willing to build and maintain the track :smile:

Are you interested in building a risc-v track? Does the MIPS track count as a RISC-V track?


Sorry, but I meant I would like to try and learn a bit about risc-v assembly.
I can’t maintain a track!
Maybe there’s someone who has the knowledge to make it happen…

Thank you for your response.!

The MIPS track says,

MIPS is a reduced instruction set computer (RISC) instruction set architecture, currently used mostly in video game consoles and routers. It is also a popular architecture in introductory courses and textbooks on computer architecture, due to its simplicity relative to x86 and ARM. Here we use the 32-bit instruction set; a 64-bit instruction set also exists.

Is that what you’re looking for?

I would like to have a place to try my hand at https://riscv.org/ assembly!

RISC-V is a RISC standard. MIPS is an implementation of RISC assembly. You can practice assembly that (very closely) implements the RISC-V standard on the MIPS track.

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Does the MIPS track count as a RISC-V track?

Sorry for necromancing a relatively old topic, but IMHO, not really.

There are several differences:

  • conditional branching instructions are different between the two (direct branching instructions in RISC-V vs. compare + branching on register set by comparison in MIPS)
  • the number of argument and temporary registers
  • separate return value and argument registers (MIPS) vs shared ones (RISC-V)

Also, MIPS (the company) stopped producing MIPS (the processor architecture) and is now a “Strategic Member” of RISC-V International:

So while they are certainly related, they are not interchangeable. RISC-V is an open ISA with a bright future whereas MIPS as an independent architecture is pretty much dead.